Position: Senior CAD Engineer – PDK, CAD Support, and Layout Automation

Job Overview:
We are seeking a highly skilled Senior CAD Engineer to support Process Design Kit (PDK) development, CAD flows, and Parameterized Cell (PCell) creation. The ideal candidate will also have expertise in layout-related CAD automation using tools such as Cadence Virtuoso and Synopsys Custom Compiler. This role requires the ability to work independently on advanced CAD and layout automation tasks while providing robust support to design teams.

Key Responsibilities:

• PDK and CAD Support:
  • Support Process Design Kit (PDK) development, updates, and integration with industry-standard EDA tools, including Cadence Virtuoso and Synopsys Custom Compiler.
  • Collaborate with foundries to ensure PDKs meet process and technology requirements, including updates to design rules and device models.
  • Debug and resolve PDK-related issues for layout, simulation, and design flows.
• Layout Automation and Customization:
  • Develop and enhance layout automation flows for Cadence Virtuoso and Synopsys Custom Compiler, focusing on improving efficiency and design accuracy.
  • Automate repetitive layout tasks using SKILL, Tcl, or Python scripting to improve designer productivity.
  • Create and maintain utilities for layout parameter extraction, rule checking, and pattern generation.
  • Support advanced layout methodologies, including full-chip layout planning, DRC optimization, and advanced node challenges.
• PCell Development and Maintenance:
  • Design and implement complex Parameterized Cells (PCells) using SKILL programming in Cadence Virtuoso.
  • Ensure PCells are reusable, robust, and aligned with design and process rules.
  • Validate and debug PCells to meet reliability and performance standards.
• CAD Flow Development and Automation:
  • Develop, customize, and maintain CAD flows for analog, digital, and mixed-signal designs.
  • Automate design validation and quality assurance processes to improve overall design productivity.
  • Collaborate with design and layout teams to implement tool customizations and improve workflow efficiency.
• Support and Collaboration:
  • Provide expert-level support to layout and design teams, addressing tool-related challenges, debugging issues, and optimizing workflows.
  • Train engineers on layout tools, automation scripts, and PDK usage.Act as a liaison between the CAD team and EDA vendors for issue resolution and tool improvements.
• Innovation and Documentation:
  • Stay updated on advancements in CAD tools, layout methodologies, and semiconductor technologies.
  • Document CAD flows, PDK updates, layout automation utilities, and best practices for internal teams.
  • Proactively identify and implement improvements in PDKs, PCells, and layout automation workflows.

Qualifications

• Education:
  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Experience:
  • 5+ years of experience in CAD support, PDK development, or layout automation.
  • Proven expertise with Cadence Virtuoso and Synopsys Custom Compiler, including automation and customization.
• Skills:
  • Proficiency in SKILL programming for PCell and layout automation in Cadence Virtuoso.
  • Experience with Tcl, Python, or Perl for layout and flow automation in Synopsys tools.
  • Strong understanding of semiconductor layout design rules, DRC/LVS verification, and advanced node challenges.
  • Familiarity with full-chip layout methodologies, including hierarchical layout planning and tapeout flows.
  • Knowledge of analog, mixed-signal, and digital design flows is a plus.
  • Strong problem-solving, communication, and documentation skills.

Key Attributes:

• Self-motivated and capable of working independently on complex CAD and layout tasks.
• Strong attention to detail and a commitment to delivering high-quality solutions.
• Ability to collaborate effectively across teams and mentor junior engineers.

This role offers an exciting opportunity to contribute to PDK development, layout automation, and CAD support in a dynamic and innovative environment, enabling cutting-edge semiconductor design.

Perks

If you’re looking to work for leaders in technology solutions who put people first, you’ve found a match. Employee First is a core value at Xinyx. We recognize that our engineers are the fulcrum of our business.

At Xinyx, we are creating a family-oriented culture and professional working environment that respects and nurtures technologists. To put Filipino engineering on the global map, we aim for our employee engagement, average tenure to be significantly higher than industry averages and for staff turnover to be lower.

How will we do it? By putting you first.

• 100% Filipino-owned and managed
• Competitive compensation
• Health insurance upon hire
• Mid-year & end-year bonuses
• Performance bonuses
• Flexi-time
• Work-life balance programs
• Company-sponsored events and outings
• ….and more